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devsupp.c

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00001 /* 00002 * $Id: devsupp.c,v 1.24 2004/01/02 04:03:21 troth Exp $ 00003 * 00004 **************************************************************************** 00005 * 00006 * simulavr - A simulator for the Atmel AVR family of microcontrollers. 00007 * Copyright (C) 2001, 2002, 2003 Theodore A. Roth 00008 * 00009 * This program is free software; you can redistribute it and/or modify 00010 * it under the terms of the GNU General Public License as published by 00011 * the Free Software Foundation; either version 2 of the License, or 00012 * (at your option) any later version. 00013 * 00014 * This program is distributed in the hope that it will be useful, 00015 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00017 * GNU General Public License for more details. 00018 * 00019 * You should have received a copy of the GNU General Public License 00020 * along with this program; if not, write to the Free Software 00021 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00022 * 00023 **************************************************************************** 00024 */ 00025 00026 /** 00027 * \file devsupp.c 00028 * \brief Contains definitions for device types (i.e. at90s8515, at90s2313, 00029 * etc.) 00030 * 00031 * This module is used to define the attributes for each device in the AVR 00032 * family. A generic constructor is used to create a new AvrCore object with 00033 * the proper ports, built-in peripherals, memory layout, registers, and 00034 * interrupt vectors, etc. 00035 */ 00036 00037 #include <config.h> 00038 00039 #include <stdio.h> 00040 #include <stdlib.h> 00041 #include <string.h> 00042 00043 #include "avrerror.h" 00044 #include "avrmalloc.h" 00045 #include "avrclass.h" 00046 #include "utils.h" 00047 #include "callback.h" 00048 #include "op_names.h" 00049 00050 #include "storage.h" 00051 #include "flash.h" 00052 00053 #include "vdevs.h" 00054 #include "memory.h" 00055 #include "stack.h" 00056 #include "register.h" 00057 #include "sram.h" 00058 #include "eeprom.h" 00059 #include "timers.h" 00060 #include "ports.h" 00061 #include "spi.h" 00062 #include "adc.h" 00063 #include "usb.h" 00064 #include "uart.h" 00065 00066 #include "avrcore.h" 00067 00068 #ifndef DOXYGEN /* don't expose to doxygen */ 00069 00070 /* 00071 * Used to select which vector table the device uses. 00072 * The value is an index into the global_vtable_list[] array 00073 * defined in intvects.c. 00074 */ 00075 enum _vector_table_select 00076 { 00077 VTAB_AT90S1200 = 0, 00078 VTAB_AT90S2313, 00079 VTAB_AT90S4414, 00080 VTAB_ATMEGA8, 00081 VTAB_ATMEGA16, 00082 VTAB_ATMEGA103, 00083 VTAB_ATMEGA128, 00084 VTAB_AT43USB355, 00085 VTAB_AT43USB320, 00086 VTAB_AT43USB325, 00087 VTAB_AT43USB324, 00088 VTAB_AT43USB326, 00089 }; 00090 00091 /* Structure for defining a supported device */ 00092 00093 typedef struct _DevSuppDefn DevSuppDefn; 00094 struct _DevSuppDefn 00095 { 00096 char *name; /* name of device type */ 00097 00098 StackType stack_type; /* STACK_HARDWARE or STACK_MEMORY */ 00099 int sram_base; /* base addr of sram */ 00100 int irq_vect_idx; /* interrupt vector table index */ 00101 00102 /* Ports is a string with two characters used to specify each port. The 00103 first char is the port id and the second is the width of the port. For 00104 example, the at90s1200 has two ports, 'b' and 'd' which are 8 and 7 00105 bits wide respectively, would be specified with a string as such: 00106 "b8d7". */ 00107 char *ports; 00108 00109 struct 00110 { 00111 int pc; /* width of program counter (usually 2, maybe 00112 3) */ 00113 int stack; /* depth of stack (only used by hardware 00114 stack) */ 00115 int flash; /* bytes of flash memory */ 00116 int sram; /* bytes of sram memory */ 00117 int eeprom; /* bytes of eeprom memory */ 00118 } size; 00119 00120 struct 00121 { /* io register function masks */ 00122 uint8_t eecr; 00123 uint8_t mcucr; 00124 uint8_t acsr; 00125 uint8_t wdtcr; 00126 uint8_t timsk; 00127 uint8_t spcr; 00128 uint8_t adcsr; 00129 uint8_t uart; 00130 uint8_t uier; 00131 } mask; 00132 }; 00133 00134 #endif /* DOXYGEN */ 00135 00136 /* *INDENT-OFF* */ 00137 00138 /* 00139 * Device Definitions 00140 */ 00141 00142 static DevSuppDefn defn_at90s1200 = { 00143 .name = "at90s1200", 00144 .stack_type = STACK_HARDWARE, 00145 .sram_base = 0, 00146 .irq_vect_idx = VTAB_AT90S1200, 00147 00148 .ports = "b8d7", 00149 00150 .size = { 00151 .pc = 2, 00152 .stack = 3, 00153 .flash = 1024, 00154 .sram = 0, 00155 .eeprom = 64 00156 }, 00157 00158 .mask = { 00159 .eecr = (mask_EERE | mask_EEWE), 00160 .mcucr = (mask_SE | mask_SM | mask_ISC01 | mask_ISC00), 00161 .acsr = (mask_ACD | mask_ACO | mask_ACI | mask_ACIE | mask_ACIS1 00162 | mask_ACIS0), 00163 .wdtcr = (mask_WDE | mask_WDP2 | mask_WDP1 | mask_WDP0), 00164 .timsk = (mask_TOIE0), 00165 .spcr = 0, 00166 .adcsr = 0, 00167 .uart = 0, 00168 .uier = 0 00169 } 00170 }; 00171 00172 static DevSuppDefn defn_at90s2313 = { 00173 .name = "at90s2313", 00174 .stack_type = STACK_MEMORY, 00175 .sram_base = SRAM_BASE, 00176 .irq_vect_idx = VTAB_AT90S2313, 00177 00178 .ports = "b8d7", 00179 00180 .size = { 00181 .pc = 2, 00182 .stack = 0, 00183 .flash = 2 * 1024, 00184 .sram = 128, 00185 .eeprom = 128 00186 }, 00187 00188 .mask = { 00189 .eecr = (mask_EERE | mask_EEWE | mask_EEMWE), 00190 .mcucr = (mask_SE | mask_SM | mask_ISC11 | mask_ISC10 00191 | mask_ISC01 | mask_ISC00), 00192 .acsr = (mask_ACD | mask_ACO | mask_ACI | mask_ACIE 00193 | mask_ACIC | mask_ACIS1 | mask_ACIS0), 00194 .wdtcr = (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 00195 | mask_WDP0), 00196 .timsk = (mask_TOIE1 | mask_OCIE1A | mask_TICIE1 00197 | mask_TOIE0), 00198 .spcr = 0, 00199 .adcsr = 0, 00200 .uart = 0, 00201 .uier = 0 00202 } 00203 }; 00204 00205 static DevSuppDefn defn_at90s4414 = { 00206 .name = "at90s4414", 00207 .stack_type = STACK_MEMORY, 00208 .sram_base = SRAM_BASE, 00209 .irq_vect_idx = VTAB_AT90S4414, 00210 00211 .ports = "a8b8c8d8", 00212 00213 .size = { 00214 .pc = 2, 00215 .stack = 0, 00216 .flash = 4 * 1024, 00217 .sram = 256, 00218 .eeprom = 256 00219 }, 00220 00221 .mask = { 00222 .eecr = (mask_EERE | mask_EEWE | mask_EEMWE), 00223 .mcucr = (mask_SRE | mask_SRW | mask_SE | mask_SM | mask_ISC11 00224 | mask_ISC10 | mask_ISC01 | mask_ISC00), 00225 .acsr = (mask_ACD | mask_ACO | mask_ACI | mask_ACIE | mask_ACIC 00226 | mask_ACIS1 | mask_ACIS0), 00227 .wdtcr = (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 00228 | mask_WDP0), 00229 .timsk = (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 00230 | mask_TOIE0), 00231 .spcr = (mask_SPIE), 00232 .adcsr = 0, 00233 .uart = ONE_UART, 00234 .uier = 0 00235 } 00236 }; 00237 00238 static DevSuppDefn defn_at90s8515 = { 00239 .name = "at90s8515", 00240 .stack_type = STACK_MEMORY, 00241 .sram_base = SRAM_BASE, 00242 .irq_vect_idx = VTAB_AT90S4414, 00243 00244 .ports = "a8b8c8d8", 00245 00246 .size = { 00247 .pc = 2, 00248 .stack = 0, 00249 .flash = 8 * 1024, 00250 .sram = 512, 00251 .eeprom = 512 00252 }, 00253 00254 .mask = { 00255 .eecr = (mask_EERE | mask_EEWE | mask_EEMWE), 00256 .mcucr = (mask_SRE | mask_SRW | mask_SE | mask_SM | mask_ISC11 00257 | mask_ISC10 | mask_ISC01 | mask_ISC00), 00258 .acsr = (mask_ACD | mask_ACO | mask_ACI | mask_ACIE | mask_ACIC 00259 | mask_ACIS1 | mask_ACIS0), 00260 .wdtcr = (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 00261 | mask_WDP0), 00262 .timsk = (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 00263 | mask_TOIE0), 00264 .spcr = (mask_SPIE), 00265 .adcsr = 0, 00266 .uart = ONE_UART, 00267 .uier = 0 00268 } 00269 }; 00270 00271 static DevSuppDefn defn_atmega8 = { 00272 .name = "atmega8", 00273 .stack_type = STACK_MEMORY, 00274 .sram_base = SRAM_BASE, 00275 .irq_vect_idx = VTAB_ATMEGA8, 00276 00277 .ports = "b8c7d8", 00278 00279 .size = { 00280 .pc = 2, 00281 .stack = 0, 00282 .flash = 8 * 1024, 00283 .sram = 1 * 1024, 00284 .eeprom = 512 00285 }, 00286 00287 .mask = { 00288 .eecr = (mask_EERE | mask_EEWE | mask_EEMWE), 00289 .mcucr = (mask_SRE | mask_SRW | mask_SE | mask_SM | mask_ISC11 00290 | mask_ISC10 | mask_ISC01 | mask_ISC00), 00291 .acsr = (mask_ACD | mask_ACO | mask_ACI | mask_ACIE | mask_ACIC 00292 | mask_ACIS1 | mask_ACIS0), 00293 .wdtcr = (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 00294 | mask_WDP0), 00295 .timsk = (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 00296 | mask_TOIE0), 00297 .spcr = (mask_SPIE), 00298 .adcsr = 0, 00299 .uart = ONE_UART, 00300 .uier = 0 00301 } 00302 }; 00303 00304 static DevSuppDefn defn_atmega16 = { 00305 .name = "atmega16", 00306 .stack_type = STACK_MEMORY, 00307 .sram_base = SRAM_BASE, 00308 .irq_vect_idx = VTAB_ATMEGA16, 00309 00310 .ports = "a8b8c8d8", 00311 00312 .size = { 00313 .pc = 2, 00314 .stack = 0, 00315 .flash = 16 * 1024, 00316 .sram = 1 * 1024, 00317 .eeprom = 512 00318 }, 00319 00320 .mask = { 00321 .eecr = (mask_EERE | mask_EEWE | mask_EEMWE), 00322 .mcucr = (mask_SRE | mask_SRW | mask_SE | mask_SM | mask_ISC11 00323 | mask_ISC10 | mask_ISC01 | mask_ISC00), 00324 .acsr = (mask_ACD | mask_ACO | mask_ACI | mask_ACIE | mask_ACIC 00325 | mask_ACIS1 | mask_ACIS0), 00326 .wdtcr = (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 00327 | mask_WDP0), 00328 .timsk = (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 00329 | mask_TOIE0), 00330 .spcr = (mask_SPIE), 00331 .adcsr = 0, 00332 .uart = ONE_UART, 00333 .uier = 0 00334 } 00335 }; 00336 00337 static DevSuppDefn defn_atmega103 = { 00338 .name = "atmega103", 00339 .stack_type = STACK_MEMORY, 00340 .sram_base = SRAM_BASE, 00341 .irq_vect_idx = VTAB_ATMEGA103, 00342 00343 .ports = "a8b8c8d8", 00344 00345 .size = { 00346 .pc = 2, 00347 .stack = 0, 00348 .flash = 128 * 1024, 00349 .sram = 4000, /* last internal address at 0x0fff */ 00350 .eeprom = 4 * 1024 00351 }, 00352 00353 .mask = { 00354 .eecr = (mask_EERE | mask_EEWE | mask_EEMWE), 00355 .mcucr = (mask_SRE | mask_SRW | mask_SE | mask_SM | mask_ISC11 00356 | mask_ISC10 | mask_ISC01 | mask_ISC00), 00357 .acsr = (mask_ACD | mask_ACO | mask_ACI | mask_ACIE | mask_ACIC 00358 | mask_ACIS1 | mask_ACIS0), 00359 .wdtcr = (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 00360 | mask_WDP0), 00361 .timsk = (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 00362 | mask_TOIE0), 00363 .spcr = (mask_SPIE), 00364 .adcsr = (mask_ADEN), 00365 .uart = ONE_UART, 00366 .uier = 0 00367 } 00368 }; 00369 00370 static DevSuppDefn defn_atmega128 = { 00371 .name = "atmega128", 00372 .stack_type = STACK_MEMORY, 00373 .sram_base = SRAM_EXTENDED_IO_BASE, 00374 .irq_vect_idx = VTAB_ATMEGA128, 00375 00376 .ports = "a8b8c8d8", 00377 00378 .size = { 00379 .pc = 2, 00380 .stack = 0, 00381 .flash = 128 * 1024, 00382 .sram = 4 * 1024, 00383 .eeprom = 4 * 1024 00384 }, 00385 00386 .mask = { 00387 .eecr = (mask_EERE | mask_EEWE | mask_EEMWE), 00388 .mcucr = (mask_SRE | mask_SRW | mask_SE | mask_SM | mask_ISC11 00389 | mask_ISC10 | mask_ISC01 | mask_ISC00), 00390 .acsr = (mask_ACD | mask_ACO | mask_ACI | mask_ACIE | mask_ACIC 00391 | mask_ACIS1 | mask_ACIS0), 00392 .wdtcr = (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 00393 | mask_WDP0), 00394 .timsk = (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 00395 | mask_TOIE0), 00396 .spcr = (mask_SPIE), 00397 .adcsr = 0, 00398 .uart = TWO_UART_HI, 00399 .uier = 0 00400 } 00401 }; 00402 00403 static DevSuppDefn defn_at43usb351 = { 00404 .name = "at43usb351", 00405 .stack_type = STACK_MEMORY, 00406 .sram_base = SRAM_BASE, 00407 .irq_vect_idx = VTAB_AT43USB355, 00408 00409 .ports = "a8b4d7", 00410 00411 .size = { 00412 .pc = 2, 00413 .stack = 0, 00414 .flash = 24 * 1024, 00415 .sram = 1 * 1024, 00416 .eeprom = 0 00417 }, 00418 00419 .mask = { 00420 .eecr = 0, 00421 .mcucr = (mask_SE | mask_SM | mask_ISC11 | mask_ISC10 00422 | mask_ISC01 | mask_ISC00), 00423 .acsr = 0, 00424 .wdtcr = (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 00425 | mask_WDP0), 00426 .timsk = (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 00427 | mask_TOIE0), 00428 .spcr = (mask_SPIE), 00429 .adcsr = (mask_ADEN), 00430 .uart = 0, 00431 .uier = (mask_FEP0 | mask_FEP1 | mask_FEP2 | mask_FEP3) 00432 } 00433 }; 00434 00435 static DevSuppDefn defn_at43usb353 = { 00436 .name = "at43usb353", 00437 .stack_type = STACK_MEMORY, 00438 .sram_base = SRAM_BASE, 00439 .irq_vect_idx = VTAB_AT43USB355, 00440 00441 .ports = "a8d7", 00442 00443 .size = { 00444 .pc = 2, 00445 .stack = 0, 00446 .flash = 24 * 1024, 00447 .sram = 1 * 1024, 00448 .eeprom = 0 00449 }, 00450 00451 .mask = { 00452 .eecr = 0, 00453 .mcucr = (mask_SE | mask_SM | mask_ISC11 | mask_ISC10 00454 | mask_ISC01 | mask_ISC00), 00455 .acsr = 0, 00456 .wdtcr = (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 00457 | mask_WDP0), 00458 .timsk = (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 00459 | mask_TOIE0), 00460 .spcr = 0, 00461 .adcsr = (mask_ADEN), 00462 .uart = 0, 00463 .uier = (mask_FEP0 | mask_FEP1 | mask_FEP2 | mask_FEP3 00464 | mask_HEP0)} 00465 }; 00466 00467 static DevSuppDefn defn_at43usb355 = { 00468 .name = "at43usb355", 00469 .stack_type = STACK_MEMORY, 00470 .sram_base = SRAM_BASE, 00471 .irq_vect_idx = VTAB_AT43USB355, 00472 00473 .ports = "a8b8d8f4", 00474 00475 .size = { 00476 .pc = 2, 00477 .stack = 0, 00478 .flash = 24 * 1024, 00479 .sram = 1 * 1024, 00480 .eeprom = 0 00481 }, 00482 00483 .mask = { 00484 .eecr = 0, 00485 .mcucr = (mask_SE | mask_SM | mask_ISC11 | mask_ISC10 00486 | mask_ISC01 | mask_ISC00), 00487 .acsr = 0, 00488 .wdtcr = (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 00489 | mask_WDP0), 00490 .timsk = (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 00491 | mask_TOIE0), 00492 .spcr = (mask_SPIE), 00493 .adcsr = (mask_ADEN), 00494 .uart = 0, 00495 .uier = (mask_FEP0 | mask_FEP1 | mask_FEP2 | mask_FEP3 00496 | mask_HEP0) 00497 } 00498 }; 00499 00500 static DevSuppDefn defn_at43usb320 = { 00501 .name = "at43usb320", 00502 .stack_type = STACK_MEMORY, 00503 .sram_base = SRAM_BASE, 00504 .irq_vect_idx = VTAB_AT43USB320, 00505 00506 .ports = "a8b8c8d8", 00507 00508 .size = { 00509 .pc = 2, 00510 .stack = 0, 00511 .flash = 32 * 1024, 00512 .sram = 512, 00513 .eeprom = 0 00514 }, 00515 00516 .mask = { 00517 .eecr = 0, 00518 .mcucr = (mask_SE | mask_SM | mask_ISC11 | mask_ISC10 00519 | mask_ISC01 | mask_ISC00), 00520 .acsr = 0, 00521 .wdtcr = (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 00522 | mask_WDP0), 00523 .timsk = (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 00524 | mask_TOIE0), 00525 .spcr = (mask_SPIE), 00526 .adcsr = 0, 00527 .uart = ONE_UART, 00528 .uier = (mask_FEP0 | mask_FEP1 | mask_FEP2 | mask_FEP3 00529 | mask_HEP0) 00530 } 00531 }; 00532 00533 static DevSuppDefn defn_at43usb324 = { 00534 .name = "at43usb324", 00535 .stack_type = STACK_MEMORY, 00536 .sram_base = SRAM_BASE, 00537 .irq_vect_idx = VTAB_AT43USB324, 00538 00539 .ports = "a8b8c8d8e2", 00540 00541 .size = { 00542 .pc = 2, 00543 .stack = 0, 00544 .flash = 16 * 1024, 00545 .sram = 512, 00546 .eeprom = 0 00547 }, 00548 00549 .mask = { 00550 .eecr = 0, 00551 .mcucr = (mask_SE | mask_SM | mask_ISC11 | mask_ISC10 00552 | mask_ISC01 | mask_ISC00), 00553 .acsr = 0, 00554 .wdtcr = (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 00555 | mask_WDP0), 00556 .timsk = (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 00557 | mask_TOIE0), 00558 .spcr = 0, 00559 .adcsr = 0, 00560 .uart = 0, 00561 .uier = (mask_FEP0 | mask_FEP1 | mask_FEP2 | mask_HEP0) 00562 } 00563 }; 00564 00565 static DevSuppDefn defn_at43usb325 = { 00566 .name = "at43usb325", 00567 .stack_type = STACK_MEMORY, 00568 .sram_base = SRAM_BASE, 00569 .irq_vect_idx = VTAB_AT43USB325, 00570 00571 .ports = "a8b8c8d7e8f4", 00572 00573 .size = { 00574 .pc = 2, 00575 .stack = 0, 00576 .flash = 16 * 1024, 00577 .sram = 512, 00578 .eeprom = 0 00579 }, 00580 00581 .mask = { 00582 .eecr = 0, 00583 .mcucr = (mask_SE | mask_SM | mask_ISC11 | mask_ISC10 00584 | mask_ISC01 | mask_ISC00), 00585 .acsr = 0, 00586 .wdtcr = (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 00587 | mask_WDP0), 00588 .timsk = (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 00589 | mask_TOIE0), 00590 .spcr = (mask_SPIE), 00591 .adcsr = 0, 00592 .uart = 0, 00593 .uier = (mask_FEP0 | mask_FEP1 | mask_FEP2 | mask_FEP3 00594 | mask_HEP0) 00595 } 00596 }; 00597 00598 static DevSuppDefn defn_at43usb326 = { 00599 .name = "at43usb326", 00600 .stack_type = STACK_MEMORY, 00601 .sram_base = SRAM_BASE, 00602 .irq_vect_idx = VTAB_AT43USB326, 00603 00604 .ports = "a8b8c8d2e6", 00605 00606 .size = { 00607 .pc = 2, 00608 .stack = 0, 00609 .flash = 16 * 1024, 00610 .sram = 512, 00611 .eeprom = 0 00612 }, 00613 00614 .mask = { 00615 .eecr = 0, 00616 .mcucr = (mask_SE | mask_SM | mask_ISC11 | mask_ISC10 00617 | mask_ISC01 | mask_ISC00), 00618 .acsr = 0, 00619 .wdtcr = (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 00620 | mask_WDP0), 00621 .timsk = (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 00622 | mask_TOIE0), 00623 .spcr = 0, 00624 .adcsr = 0, 00625 .uart = 0, 00626 .uier = (mask_FEP0 | mask_FEP1 | mask_FEP2 | mask_HEP0) 00627 } 00628 }; 00629 00630 /* *INDENT-ON* */ 00631 00632 /** \brief List of supported devices. */ 00633 00634 static DevSuppDefn *devices_supported[] = { 00635 &defn_at90s1200, 00636 &defn_at90s2313, 00637 &defn_at90s4414, 00638 &defn_at90s8515, 00639 &defn_atmega8, 00640 &defn_atmega16, 00641 &defn_atmega103, 00642 &defn_atmega128, 00643 &defn_at43usb351, 00644 &defn_at43usb353, 00645 &defn_at43usb355, 00646 &defn_at43usb320, 00647 &defn_at43usb324, 00648 &defn_at43usb325, 00649 &defn_at43usb326, 00650 NULL 00651 }; 00652 00653 /* 00654 * Private. 00655 * 00656 * Look up a device name in support list. 00657 * 00658 * Returns pointer to DevSuppDefn or NULL if not found. 00659 */ 00660 static DevSuppDefn * 00661 dev_supp_lookup_device (char *dev_name) 00662 { 00663 DevSuppDefn **dev = devices_supported; 00664 int len; 00665 00666 while ((*dev)) 00667 { 00668 len = strlen ((*dev)->name); 00669 00670 if (strncmp ((*dev)->name, dev_name, len) == 0) 00671 return (*dev); 00672 00673 dev++; 00674 } 00675 return NULL; 00676 } 00677 00678 /** \brief Print a list of supported devices to a file pointer. */ 00679 00680 void 00681 dev_supp_list_devices (FILE * fp) 00682 { 00683 DevSuppDefn **dev; 00684 00685 for (dev = devices_supported; (*dev); dev++) 00686 fprintf (fp, " %s\n", (*dev)->name); 00687 } 00688 00689 /** 00690 * \brief Creates a new core. 00691 * 00692 * This constructs an AVR CPU with the characteristics of the device passed 00693 * in as dev_name. It is sort of the master constructor for a core. 00694 * 00695 * \return A pointer to an AVR core with properties of dev_name 00696 */ 00697 00698 AvrCore * 00699 dev_supp_create_core (char *dev_name) 00700 { 00701 AvrCore *core = NULL; 00702 DevSuppDefn *dev = dev_supp_lookup_device (dev_name); 00703 VDevice *vdev; 00704 Timer16_T *timer16; 00705 char *pp; 00706 00707 if (dev) 00708 { 00709 fprintf (stderr, "\nSimulating a %s device.\n\n", dev->name); 00710 00711 /* Create the base core object */ 00712 core = 00713 avr_core_new (dev->size.flash, dev->size.pc, dev->stack_type, 00714 dev->size.stack, dev->irq_vect_idx); 00715 00716 /* all devices have a timer/counter 0 */ 00717 avr_core_attach_vdev (core, (VDevice *)timer0_new ()); 00718 00719 /* Attach device specific vdevs */ 00720 00721 if (dev->size.sram > 0) 00722 { 00723 vdev = (VDevice *)sram_new (dev->sram_base, dev->size.sram); 00724 avr_core_attach_vdev (core, vdev); 00725 } 00726 00727 if (dev->size.eeprom > 0) 00728 { 00729 vdev = (VDevice *)eeprom_new (dev->size.eeprom, dev->mask.eecr); 00730 avr_core_attach_vdev (core, vdev); 00731 } 00732 00733 if (dev->mask.mcucr) 00734 { 00735 vdev = (VDevice *)mcucr_new (dev->mask.mcucr); 00736 avr_core_attach_vdev (core, vdev); 00737 } 00738 00739 if (dev->mask.acsr) 00740 { 00741 vdev = (VDevice *)acsr_new (dev->mask.acsr); 00742 avr_core_attach_vdev (core, vdev); 00743 } 00744 00745 if (dev->mask.wdtcr) 00746 { 00747 vdev = (VDevice *)wdtcr_new (dev->mask.wdtcr); 00748 avr_core_attach_vdev (core, vdev); 00749 } 00750 00751 if (dev->mask.timsk & mask_TOV0) 00752 { 00753 vdev = (VDevice *)timer_intr_new (dev->mask.timsk); 00754 avr_core_attach_vdev (core, vdev); 00755 } 00756 00757 if (dev->mask.spcr) 00758 { 00759 vdev = (VDevice *)spi_intr_new (); 00760 avr_core_attach_vdev (core, vdev); 00761 vdev = (VDevice *)spi_new (); 00762 avr_core_attach_vdev (core, vdev); 00763 } 00764 00765 if (dev->mask.timsk & mask_TOV1) 00766 { 00767 timer16 = timer16_new (global_timer16_defs[TD_TIMER1]); 00768 avr_core_attach_vdev (core, (VDevice *)timer16); 00769 00770 if (dev->mask.timsk & mask_OCF1A) 00771 { 00772 timer16->ocra = ocreg16_new (global_ocreg16_defs[OCR1A_DEF]); 00773 avr_core_attach_vdev (core, (VDevice *)timer16->ocra); 00774 } 00775 00776 if (dev->mask.timsk & mask_OCF1B) 00777 { 00778 timer16->ocrb = ocreg16_new (global_ocreg16_defs[OCR1B_DEF]); 00779 avr_core_attach_vdev (core, (VDevice *)timer16->ocrb); 00780 } 00781 } 00782 00783 if (dev->mask.adcsr) 00784 { 00785 vdev = (VDevice *)adc_intr_new (dev->mask.uier); 00786 avr_core_attach_vdev (core, vdev); 00787 vdev = (VDevice *)adc_new (dev->mask.uier); 00788 avr_core_attach_vdev (core, vdev); 00789 } 00790 00791 if (dev->mask.uart) 00792 { 00793 vdev = (VDevice *)uart0_intr_new (dev->mask.uart); 00794 avr_core_attach_vdev (core, vdev); /* uart0_intterupt */ 00795 00796 if (dev->mask.uart & TWO_UART) 00797 { 00798 vdev = (VDevice *)uart_new (ONE_UART); 00799 avr_core_attach_vdev (core, vdev); /* this is for uart0 */ 00800 vdev = (VDevice *)uart1_intr_new (dev->mask.uart); 00801 avr_core_attach_vdev (core, vdev); /* uart1_intterupt */ 00802 } 00803 vdev = (VDevice *)uart_new (dev->mask.uart); 00804 avr_core_attach_vdev (core, vdev); /* this is for uart0/uart1 */ 00805 } 00806 00807 if (dev->mask.uier) 00808 { 00809 vdev = (VDevice *)usb_intr_new (dev->mask.uier); 00810 avr_core_attach_vdev (core, vdev); 00811 vdev = (VDevice *)usb_new (); 00812 avr_core_attach_vdev (core, vdev); 00813 } 00814 00815 /* Attach device port vdevs */ 00816 00817 pp = dev->ports; 00818 while (*pp) 00819 { 00820 VDevice *port = NULL; 00821 int width = 0; 00822 00823 /* Get the width of the port */ 00824 switch (pp[1]) 00825 { 00826 case '1': 00827 width = PORT_1_BIT; 00828 break; 00829 case '2': 00830 width = PORT_2_BIT; 00831 break; 00832 case '3': 00833 width = PORT_3_BIT; 00834 break; 00835 case '4': 00836 width = PORT_4_BIT; 00837 break; 00838 case '5': 00839 width = PORT_5_BIT; 00840 break; 00841 case '6': 00842 width = PORT_6_BIT; 00843 break; 00844 case '7': 00845 width = PORT_7_BIT; 00846 break; 00847 case '8': 00848 width = PORT_8_BIT; 00849 break; 00850 default: 00851 avr_error ("Invalid port width: port=%c, width=%c", pp[0], 00852 pp[1]); 00853 } 00854 00855 /* Create the port VDevice */ 00856 switch (pp[0]) 00857 { 00858 case 'a': 00859 case 'A': 00860 port = (VDevice *)porta_new (width); 00861 break; 00862 case 'b': 00863 case 'B': 00864 port = (VDevice *)portb_new (width); 00865 break; 00866 case 'c': 00867 case 'C': 00868 port = (VDevice *)portc_new (width); 00869 break; 00870 case 'd': 00871 case 'D': 00872 port = (VDevice *)portd_new (width); 00873 break; 00874 case 'e': 00875 case 'E': 00876 port = (VDevice *)porte_new (width); 00877 break; 00878 case 'f': 00879 case 'F': 00880 port = (VDevice *)portf_new (width); 00881 break; 00882 default: 00883 avr_error ("Invalid port id: port=%c", pp[0]); 00884 } 00885 avr_core_attach_vdev (core, port); 00886 pp += 2; 00887 } 00888 } 00889 00890 return core; 00891 }

Automatically generated by Doxygen 1.3.8 on 11 Aug 2004.